Exploration of Reconfigurable Architectures - ERA

  

(Project funded by National ICT R&D Fund)

Project Title Design & Development of Application-Specific FPGA/Reconfigurable Hardware Generator
Funding Organization ICTRnD Fund
Project Directors Dr. M. Mohiuddin, Dr. Husain Parvez
Budget 13.4 million PKR
Duration 24 months
Start date June 2012
Location Embedded Systems Research Group @ PAF-KIET
Contact US husain.parvez@pafkiet.edu.pk
 
  1. Executive summary
  2. Team members
  3. Technical progress reports submitted
  4. Project deliverables submitted
  5. News

Executive summary

 

The Field Programmable Gate Arrays (FPGAs) are well known for their hardware flexibility which makes it possible and extremely simple to modify designs quickly, frequently and as late as desired in the design cycle. Low volume production of FPGA-based products is effective and economical because they are easy to design and program in shortest possible time. The generic reconfigurable resources in an FPGA can be programmed to execute a vast variety of applications. However, this very flexibility of FPGAs makes them much larger, slower, and more power consuming than their counterpart ASICs (Application Specific Integrated Circuits) and ASSPs (Application Specific Standard Products). Consequently, FPGAs are unsuitable for applications requiring high volume production, high performance or low power consumption. Therefore, despite enormous benefits of flexibility, the global FPGA revenues in the year 2009 were only 3.3 billion dollars compared to 88 billion dollar revenues of ASICs and ASSPs.

 

We propose to design a GUI (Graphical User Interface)-based software platform which can be used to design, explore and generate application-specific FPGA and similar reconfigurable architectures. These alternate FPGA (reconfigurable) architectures can be optimized for target applications in terms of area, speed and/or power consumption. The output of this tool will be VHDL files of the optimized FPGA architecture which can be translated into GDSII format files for fabrication using third-party tools. This platform will also map application circuits on the architecture through advanced mapping algorithms and will generate their bitstreams (binary files). These application circuits encompass fields as diverse as data and telecommunication, security, multimedia, medical, and other real-time Digital Signal Processing (DSP) systems. 

 

This project explores new and innovative FPGA/Reconfigurable architectures which have improved area, speed and power consumption performance as compared to traditional FPGA architectures. Different architectures explored in this project will become part of a GUI-based reconfigurable hardware generator.

 

Architectures supported by this platform will be

  • Traditional Mesh-based Heterogeneous FPGA architecture: A traditional FPGA architecture consisting of a regular mesh-based configurable routing network, configurable logic blocks, and hard-blocks such as Adders, Multipliers, RAMs, dedicated DSP blocks etc. 
     
  • Application Specific Inflexible FPGA (ASIF): An ASIF is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at mutually exclusive times. A set of user application circuits can be quickly mapped on an FPGA for prototypical design. Later, for high volume production, it can be migrated to an ASIF, which can be reprogrammed, though at a limited scale, to execute new or modified application circuits.
     
  • Regular ASIF architecture: A regular ASIF will have less layout complications and increased reconfigurability at the expense of increased area. A compromise solution needs to be searched for ASIF architectures having minimum area, maximum reconfigurability, and minimum layout complications. A regular ASIF solution tends to be closer to an FPGA than to an ASIC in its architecture.
     
  • FPGA to ASIC: Multiple application circuits are mapped onto an FPGA. Later for high volume production, high performance and/or reduced area, FPGA-based solution is reduced to an ASIC solution. This ASIC will support multiple application circuits which can be easily switched when required by the user.
     
  • Reconfigurable Network on Chip (NoC): The reconfigurable NoC will consist of time multiplexed routing network, general-purpose microprocessors, and other generic reconfigurable resources. Time critical portions of user application circuits will be implemented on reconfigurable resources; non-time critical portions will be implemented on general purpose microprocessors. This work can lay the grounds to continue research on Hardware-Software co-design of embedded systems.
 

Team members

 

Project Directors

  1. Dr. Muhammad Mohiuddin, PI
  2. Dr. Husain Parvez, CPI

Senior Developers

  1. Fateen Mubarak
  2. Absar Ansari

Research Assistants

  1. Baqar Raza
  2. Ali Asghar
  3. Muhammad Ameen Qureshi
  4. Faisal Riaz
  5. Muhammad Mazhar Iqbal
  6. Waqar Ahmed
  7. Maarij Rahim
  8. Sanjay Kumar
  9. Muhammad Usman
  10. Sohail Ibrahim

Undergraduate students

  1. Muddasir Soomro
  2. Aqib Saeed

Miscellaneous Staff

  1. Sadat Khan, Coordinator
  2. Muhammad Ahmed, Accountant
 

Technical progress reports submitted

 

  1. First Quarterly Report, 10th October 2012 
  2. Second Quarterly Report, 12th Feburary 2013
  3. Third Quarterly Report, 23rd April 2013
  4. Fourth Quarterly Report, 22nd July 2013
  5. Fifth Quarterly Report, 25th October 2013
  6. Sixth Quarterly Report, 12th May, 2014
  7. Seventh Quarterly Report, 22nd July, 2014
 

Project deliverables submitted

 

First Quarterly deliverables submitted, 10th October 2012

  1. Software Version-1 (VERA Back-end)
  2. Test-bench circuits Version-1 (MCNC)
  3. Release document Version-1

Second Quarterly deliverables submitted, 12th Feburary 2013

  1. Software Version-2 (VERA Front-end)
  2. Documentation Version-1 (VERA Back-end, VERA Front-end)
  3. Comparison Results Version-1 (FPGA, ASIF)

Third Quarterly deliverables submitted, 23rd April 2013

  1. Quartus-based Software flow for converting VHDL to NET
  2. Test-bench circuits Version-2 (SET-A)
  3. Documentation Version-2

Poster deliverable submitted, 1st July 2013

Fourth Quarterly deliverables submitted, 22nd July 2013

  1. Software Version-3 (VERA Front-end)
  2. Comparison results

Fifth Quarterly Report, 25th October 2013

  1. Test-bench circuits Version-3
  2. Comparison results

Sixth Quarterly Report, 12th May, 2014

  1. Software (GUI) Version-4
  2. Documentation Version-3

Seventh Quarterly Report, 22nd July, 2014

  1. Documentation Version-4

 

 

News

  1. Research paper submitted at FPL 2013 (paper not accepted, but got some valuable comments)
  2. Two research papers submitted at ICFPT 2013 (paper not accepted, but got some valuable comments)
  3. One research paper accepted and published at Applied Reconfigurable Computing (ARC), April 2014, Portugal.
  4. One research paper accepted and published at 1st International Young Engineers Convention, IYEC 2014, April 2014, UET Lahore.
  5. Two research papers accepted and published at Reconfigurable Communication-centric Systems-on-Chip (ReCoSoc), May 2014, Montpellier, France.
  6. One paper submitted at Journal of Circuits, Systems and Computers.  (paper not accepted, but got some valuable comments)